In a digital TV receiver, a broadcast analog color video signal is applied to a conventional receiving antenna. The signal received by the antenna is processed by an analog tuner and intermediate frequency (IF) circuitry. A baseband composite video signal CVS from the IF circuitry is applied to an analog-to-digital (A/D) converter. The A/D converter develops digital representations of the analog, baseband composite video signal CVS in response to a sampling or master clock signal MCS. The digital samples are processed in digital circuits to appropriately condition the luminance Y and chrominance C components of the composite video signal CVS for application to the matrix circuits of the TV receiver. The Red (R), Green (G) and Blue (B) signals developed by the matrix circuits are converted back to the analog format for application to the display device.
For chroma demodulation, it is advantageous to set the frequency of the sampling clock signal MCS at four (4) times the color subcarrier rate F.sub.SC, and to phase lock the 4 F.sub.SC clock signal to the color burst signal BS incorporated in the incoming composite video signal CVS. Sampling the chrominance signal using a 4 F.sub.SC burst locked clock (BLC) produces the following sample sequence: -(B-Y),-(R-Y),(B-Y),(R-Y),-(B-Y) and so on. Demodulation may be accomplished by merely demultiplexing the above sample sequence into separate R-Y and B-Y data streams.
However, for memory based features (e.g., pix-in-pix, freeze picture, zoom, recursive filtering, etc.), it is desirable to process the video signal with a line locked clock (LLC). A line locked clock produces a fixed integer number (e.g., 910 in the NTSC format) of sampling points per horizontal line. This simplifies memory based video features processing (e.g., line, field or frame memories), because the respective samples are vertically aligned (i.e., TV raster is orthogonally sampled).
For a standard NTSC video signal (e.g., broadcast TV signal), a sampling clock frequency, which is an even integer multiple of the color subcarrier frequency F.sub.SC, contains a fixed integer number of clock pulses in every horizontal line period. The color subcarrier frequency F.sub.SC is established at 455/2 times the horizontal line frequency F.sub.H (i.e., F.sub.SC =(455/2).multidot.F.sub.H) in a standard NTSC TV Signal. A sampling clock frequency F.sub.MCS of 4 F.sub.SC has exactly 910 clock periods (4.times.455/2) in every horizontal line period. For a standard NTSC video signal, a clock signal may be concurrently burst locked and line locked, thereby facilitating both chroma demodulation and memory based applications (e.g., zoom).
However, not all NTSC compatible TV signals conform precisely to the NTSC standard format. For example, signals produced by a video cassette recorder (VCR) have varying horizontal line periods in the reproduced signal. This results in a variation in the number of clock pulses developed per horizontal line (e.g., 909.9, 910, 910.1, etc.). In general, for non-standard TV signals, it is not possible that a clock signal be simultaneously burst locked and line locked.
One previously known approach for processing non-standard TV signals in the digitial domain employs a burst locked clock. The use of a burst locked clock simplifies chroma demodulation. However, a burst locked clock produces a variation in the number of clock pulses per horizontal line, and, therefore, causes a line-to-line variation in the phase of the clock signal relative to the incoming horizontal synchronizing signal IHSS. The line-to-line timing or phase variation (i.e., skew errors) of the clock signal relative to the horizontal sync signal causes line-to-line misalignment of the picture elements (pixels) displayed on the TV screen, thereby requiring skew correction for memory-based features.
In order to compensate for the line-to-line misalignment of the pixels before they are written into the memory in a burst locked clock system, the input signal samples are time shifted or skew corrected for the phase differences between the incoming horizontal sync signal IHSS and the sampling clock signal MCS. Additionally, the signal samples read out from the memory are corrected for skew errors prior to their application to the matrix circuits of the TV receiver. U.S. Pat. No. 4,638,360, issued to Christopher, et al., and entitled "TIMING CORRECTION FOR A PICTURE-IN-PICTURE TELEVISION SYSTEM", describes illustrative circuitry, responsive to a skew signal SS, for correcting skew errors in the incoming and outgoing signals in a memory-based video signal processing system, which uses a burst locked clock.
Another approach for processing non-standard TV signals in the digital domain uses an asynchronous or free-running clock. An advantage of an asynchronous clock system is that complicated circuitry (e.g., including a voltage controlled oscillator or VCO) is not required for locking the phase of the clock signal with the color burst phase. However, an asynchronous clock system requires skew correction for memory-based features when non-standard video signals are processed. Another disadvantage of an asynchronous clock system is that chroma demodulation is more complicated.
A skew measuring circuit for determining the phase errors (also known as timing or skew errors) between the clock signal and the incoming horizontal sync signal IHSS is described in detail in a commonly-assigned, copending U.S. patent application Ser. No. 761,179, entitled "TIMING CORRECTION CIRCUITRY AS FOR TV SIGNAL RECURSIVE FILTERS", and filed in behalf of Willis, et al (now U.S. Pat. No. 4,667,240). An integral circuit (IC) wich includes a functionally similar skew measuring circuit is the Deflection Processor Unit (DPU2532) referred to in the ITT data book "DIGIT 2000 NTSC DOUBLE-SCAN VLSI DIGITAL TV SYSTEM" , published by ITT Intermetall Semiconductors, Freiburg, W. Germany.